Base class for SPI bus information.
The connection settings of a device on a SPI bus.
The communications channel to a device on a SPI bus.
Exception thrown when a check in driver's constructor finds a device that already exists with the same settings (SPI bus AND chip select line)
Specifies order in which bits are transferred first on the SPI bus.
Defines the bus configuration between the master and the slave device.
Defines how data is synchronized between devices on a SPI bus. Clock Polarity (CPOL) determines if clock signal is low or high when in idle state. Clock Phase (CPHA) determines when data is sampled relative to the clock signal.
Defines the sharing mode for the SPI bus.